| PART |
Description |
Maker |
| CY23EP05SXI-1T CY23EP05SXC-1HT CY23EP05SXI-1HT CY2 |
2.5 V or 3.3 V,10-220-MHz, Low Jitter, 5 Output Zero Delay Buffer
2.5V or 3.3V,10- 220 MHz, Low Jitter, 5 Output Zero Delay Buffer 23EP SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
|
Cypress Semiconductor, Corp.
|
| ICS2309 ICS2309G-1H ICS2309G-1HLF ICS2309G-1HLFT I |
3.3 VOLT ZERO DELAY / LOW SKEW BUFFER
3.3 Volt Zero Delay, Low Skew Buffer
From old datasheet system
|
ICST[Integrated Circuit Systems]
|
| 1505 1505-50B 1505-50G 1505-5B 1505-50A 1505-50C 1 |
Delay 300 /-15 ns, 5-TAP SIP delay line Td/Tr=3
Delay 100 /-5 ns, 5-TAP SIP delay line Td/Tr=3
Delay 60 /-3 ns, 5-TAP SIP delay line Td/Tr=3
Delay 30 /-2 ns, 5-TAP SIP delay line Td/Tr=3
Fixed 5-tap passive SIP delay line
PASSIVE DELAY LINE, TRUE OUTPUT, PSIP7
Delay 70 /-3.5 ns, 5-TAP SIP delay line Td/Tr=3
Delay 75 /-3.5 ns, 5-TAP SIP delay line Td/Tr=3
Delay 90 /-5 ns, 5-TAP SIP delay line Td/Tr=3
Delay 40 /-2.5 ns, 5-TAP SIP delay line Td/Tr=3
Delay 50 /-3 ns, 5-TAP SIP delay line Td/Tr=3
Delay 20 /-1.5 ns, 5-TAP SIP delay line Td/Tr=3
Delay 200 /-10 ns, 5-TAP SIP delay line Td/Tr=3
Delay 5 /-1 ns, 5-TAP SIP delay line Td/Tr=3
|
DATA DELAY DEVICES INC
|
| UPD424280LLE-A80 UPD424280LLE-A70 UPD424280AG5M-80 |
x18 Fast Page Mode DRAM
Quad PLL Clock Generator with Serial Interface (I2C)
Low-Cost 3.3V Spread Aware™ Zero Delay Buffer
MediaClock™ MPEG Clock Generator with VCXO
MediaClock™ PDP Clock Generator
Field and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction
HOTLink II™ SMPTE Receiver Training Clock
3.3V Zero Delay Buffer x18快速页面模式的DRAM
|
|
| W132 |
Spread Aware/ Ten/Eleven Output Zero Delay Buffer
From old datasheet system
Spread Aware, Ten/Eleven Output Zero Delay Buffer
|
Cypress Semiconductor
|
| CY2304SXC-1T CY2304SXI-1T |
3.3 V Zero Delay Buffer
|
Cypress
|
| CY2308SXI-1HT CY2308ZXC-1HT CY2308SXI-2T |
3.3 V Zero Delay Buffer
|
Cypress
|
